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Prof. Mayank Shrivastava

Our Instructor

Prof. Mayank Shrivastava

  • Responsibility:Professor
  • Email:mayank@iisc.ac.in
  • Years in IISc:
  • Total PhD Graduated:
  • Total Journal Papers:
  • Total Conference Papers:
  • Total Patents:

Research Thrust:

Top 20% Publications:

  1. Chapter titled “Towards Drain extended FinFETs for SoC applications” in book “Toward Quantum FinFET”, edited by Weihua Han and Zhiming M. Wang, Springer, Dec. 2013, ISBN 978-3-319-02021-1.
  2. Mayank Shrivastava and V. Ramgopal Rao, “Tunnel Field Effect Transistors”, Present, Past and Future, Technical Brief appeared in the IEEE EDS Newsletters, July 2016 (Cover page article).
  3. Mohammad Munshi Ateeb, Mehak Mir Ashraf and Mayank Shrivastava, “Distinct Breakdown Mechanisms Under DC and Pulsed Conditions in AlGaN/GaN HEMTs with Floating Substrate Termination”, to appear in IEEE Transactions on Electron Devices.
  4. Mehak Mir Ashraf, Vipin Joshi, Mohammad Ateeb Munshi, Anup Vitthal Thakare, Rajarshi Roy Chaudhuri and Mayank Shrivastava, “Improving Threshold Voltage and its Stability in p-GaN Gated HEMTs by Mechanical Stress Engineering”, to appear in IEEE Transactions on Electron Devices.
  5. Rasik Rashid Malik, Rajarshi Roy Chaudhuri, Vipin Joshi, and Mayank Shrivastava, “Physical Insights into Turn-ON Mechanisms in p-GaN Gate AlGaN/GaN HEMTs – Part I”, to appear in IEEE Transactions on Electron Devices.
  6. Rasik Rashid Malik, Vipin Joshi, Saniya Syed Wani, Simran R Karthik, Rajarshi Roy Chaudhuri, Avinas N Shaji, Zubear Khan, and Mayank Shrivastava, “Unique Surface Passivation Stoichiometry Dependence of Dynamic ON Resistance and Its Suppression in p-GaN Gate AlGaN/GaN HEMTs,” to appear in IEEE Transactions on Electron Devices.
  7. Aadil Bashir Dar, Adil Meersha, Amogh K. M, Asif A. Shah, Anand Kumar Rai, Rupali Verma, Utpreksh Patbhaje, Jeevesh Kumar and Mayank Shrivastava, “Physical Insights Into the Effect of Substrate on Graphene RF Transistor Performance and Demonstration of Novel Inverted T-Gate Architecture”, in IEEE Journal of the Electron Devices Society, Vol. 13, pp. 930-936, 2025, doi: 10.1109/JEDS.2025.3591152
  8. Rupali Verma, Utpreksh Patbhaje, & Mayank Shrivastava, “In-plane Field Enabled Dissociation Dynamics of Defect Bound Excitons and Excitonic Oscillator Strength Redistribution in Monolayer WS2”, accepted in ACS Nano.
  9. Utpreksh Patbhaje, Rupali Verma, Jeevesh Kumar, Ansh & Mayank Shrivastava, “Unveiling Inverse Piezoelectricity & Field Induced Nonvolatile Strain in 2D TMDs”, accepted in Nature, npj 2D Materials and Applications, May 2025.
  10. Mohammad Munshi Ateeb, Mehak Mir Ashraf & Mayank Shrivastava, “Enhanced ESD Reliability of AlGaN/GaN MIS-HEMTs using a p-type Oxide Passivation”, IEEE Transactions on Electron Devices, Volume: 72, Issue: xx, xx 2025.
  11. Harsh Raj, Rajarshi Roy Chaudhuri and Mayank Shrivastava, “Understanding the DC Reverse Bias Conduction and Breakdown Mechanisms in β− Ga2O3 Schottky Barrier Diodes”, IEEE Transactions on Electron Devices, Volume: 72, Issue: xx, xx 2025.
  12. Aakanksha Mishra, M. Monishmurali, B. Sampath Kumar, Shaik Ahamed Suzaad, Shubham Kumar, Kiran Pote Sanjay, Amit Kumar Singh, Avinash Singh, Ankur Gupta, and Mayank Shrivastava, “Extremely High ESD Failure Voltage of RESURF LDMOS Devices for ESD Resilient Driver Applications”, IEEE Transactions on Electron Devices, Volume: 72, Issue: 5, May 2025, DOI: 10.1109/TED.2025.3556114
  13. Rupali Verma, Utpreksh Patbhaje, Asif Shah, Aadil Dar, and Mayank Shrivastava, “Impact Ionization and the Paradox of Defects in Transition Metal Dichalcogenide FETs”, Nature, npj 2D Materials and Applications, Jan 2025. DOI: https://doi.org/10.1038/s41699-024-00521-5
  14. Asif Shah, Aadil Dar, and Mayank Shrivastava, “Revisiting the Origin of Non-Volatile Resistive Switching in MoS2 Atomristor”, Nature, npj 2D Materials and Applications, 8, 80 (2024). https://doi.org/10.1038/s41699-024-00518-0
  15. Anand Kumar Rai, Asif A. Shah, Aadil Bashir Dar, Jeevesh Kumar, Mayank Shrivastava, “Reconfiguration of Intrinsic Depletion-Mode Characteristics of MoS2 Field-Effect Transistors to High-performance Enhancement-Mode Operation Using an Argon Plasma-Induced p-Type Doping Technique”, Small Methods 2024, 2401001, https://doi.org/10.1002/smtd.202401001
  16. M. A. Munshi, M. A. Mir, Vipin Joshi, R. R. Chaudhuri, Rasik Malik and Mayank Shrivastava, “Temperature-Dependent ESD Breakdown in AlGaN/GaN HEMTs With Carbon-Doped Buffer,” IEEE Transactions on Electron Devices, Volume: 71, Issue: 11, November 2024, DOI: 10.1109/TED.2024.3462375
  17. M. A. Mir, Vipin Joshi, R. R. Chaudhuri, M. A. Munshi, Rasik Malik and Mayank Shrivastava, “Physical Insights Into the Drain Current Injection-Induced Device Instabilities in AlGaN/GaN HEMTs,” IEEE Transactions on Electron Devices, vol. 71, no. 9, 2024, pp. 5251-5257. https://doi.org/10.1109/TED.2024.3427097
  18. Bidisha Nath, Rajarshi Roy Chaudhuri, Mayank Shrivastava, Praveen C Ramamurthy, Debiprosad Roy Mahapatra, Gopalkrishna Hegde, “Role of transition metal iodides in defect and charge dynamics of perovskite solar cells,” Solar Energy, vol. 282, 2024, p. 112928. https://doi.org/10.1016/j.solener.2024.112928
  19. Shivangi Srivastava, Anand Kumar Rai, Mayank Shrivastava, Praveen C. Ramamurthy, “Sub-100 nm Patterning of P3HT with Enhanced OFET Device Performance by Dose Optimization of Electron Beam-Induced Cross-Linking,” ACS Applied Electronic Materials, vol. 6, no. 8, 2024, pp. 5923-5933. https://doi.org/10.1021/acsaelm.4c00904
  20. Anand Kumar Rai, Asif A. Shah, Jeevesh Kumar, Sumana Chattaraj, Aadil Bashir Dar, Utpreksh Patbhaje, and Mayank Shrivastava, “Contact Doping, Defect Passivation and Performance Enhancement of MoS2 FETs via Fluorine Ion Introduction in Contacts & its Cyclic Field-Assisted Activation”, ACS Nano 2024, 18, 8, 6215–6228. DOI: https://doi.org/10.1021/acsnano.3c09428
  21. Jatin, M. Monishmurali, and Mayank Shrivastava, “On the Multi-Finger Turn-on Instability in Drain Extended Vertically Stacked Nanosheet FETs Under ESD Stress Conditions”, IEEE Transactions on Electron Devices, Volume: 71, Issue: 2, February 2024. DOI: 10.1109/TED.2023.3347708
  22. Kuruva Hemanjaneyulu, Jeevesh Kumar, and Mayank Shrivastava, “Enhanced Carrier Injection Across S/D Contacts in Selenium Based TMD FETs Using KI & Metal Induced Gap-States Engineering”, IEEE Journal of Electron Devices, Vol. 12, Jan. 2024, pp: 46-50. DOI: 10.1109/JEDS.2023.3345020

Media Coverage:

Patents and Stats:

Patents

  1. Rajesh Thakkar, Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, M. B. Patil, “Operational Amplifier Having Improved Slew Rate ” United States Patent (03-01-2012) 8,089,314 (Also filed/granted in other countries, India: 542/MUM/2010, European Patent: EP2543141; Chinese Patent: CN102474230; and PCT: WO2011107824)
  2. Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, “Nonvolatile floating gate analog memory cell”, United States Patent (07-05-2013) 8,436,413 (Also filed/granted in other countries, Indian Patent No 258773; and PCT: WO2010046922.)
  3. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei,” Semiconductor devices with trench isolations”, United States Patent (17-01-2012) 8,097,930 (Also granted in Germany, Patent No: DE102009034405)
  4. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, “Field-effect device and manufacturing method thereof”, United States Patent (15-01-2013) 8,354,710 (Also granted in Germany, Patent No: DE102009030086)
  5. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, Ramgopal Rao, Christian Russ, “Device and method for coupling first and second device portions”, United States Patent (04-06-2013) 8,455,947  (Also granted in Germany, Patent No: DE102010000355)
  6. Mayank Shrivastava, Christian Russ, Harald Gossner, V. Ramgopal Rao, “Drain extended field effect transistors and methods of formation thereof”, United States Patent (17-09-2013) 8,536,648  (Also granted in Germany, Patent No: DE102012100767)
  7. Mayank Shrivastava and Harald Gossner, “Drain extended MOS device for Bulk FinFET technology”, United States Patent (14-01-2014) 8,629,420 (Also granted in Germany, Patent No: DE102013106152; Taiwan, Patent No: TW201411844 and in China, Patent No: CN103531633)
  8. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, “Semiconductor devices and methods for manufacturing a semiconductor device”, United States Patent (04-02-2014) 8,643,090 (Also granted in Germany, Patent No: DE102010016000)
  9. Mayank Shrivastava, Christian Russ, Harald Gossner, “Low voltage ESD clamping using high voltage devices”, United States Patent (18-02-2014) 8,654,491 (Also granted in Germany, Patent No: DE102013103076; and in China, Patent No: CN107424988)
  10. Mayank Shrivastava, Maryam Shojaei Baghini, Christian Russ, Harald Gossner, Ramgopal Rao, “High voltage semiconductor devices”, United States Patent (04-03-2014) 8,664,720 (Also granted in Germany, Patent No: DE102011050958)
  11. Mayank Shrivastava, Christian Russ, Harald Gossner, “Selective current pumping to enhance low-voltage ESD clamping using high voltage devices”, United States Patent (25-03-2014) 8,681,461 (Also granted in Germany, Patent No: DE102013103076 and in China, Patent No: CN103367357)
  12. Mayank Shrivastava and Harald Gossner, “Silicon controlled rectifier (SCR) device for bulk FinFET technology”, United States Patent (22-07-2014) 8,785,968 (Also granted in Taiwan, Patent No: TW201423957)
  13. Mayank Shrivastava, Christian Russ and Harald Gossner, “Tunable Fin-SCR for Robust ESD Protection”, United States Patent (24-02-2015) 8,963,201.
  14. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, “Field-Effect Device and Manufacturing Method Thereof”, United States Patent (19-05-2015) 9,035,375 (Also granted in Germany, Patent No: DE102009030086)
  15. Mayank Shrivastava, Christian Russ, Harald Gossner, V. Ramgopal Rao, “Drain Extended Field Effect Transistors and Methods of Formation Thereof”, United States Patent (21-07-2015) 9,087,892 (Also granted in Germany, Patent No: DE102012100767).
  16. Mayank Shrivastava and Christian Russ, “Semiconductor devices and arrangements for electrostatic (ESD) protection”, United States Patent (31-05-2016) 9,356,013.
  17. Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner, Ramgopal Rao, “Methods for manufacturing a semiconductor device”, United States Patent (14-06-2016) 9,368,573 (Also granted in Germany, Patent No: DE102010016000)
  18. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, “Field-effect device and manufacturing method thereof”, United States Patent (26-07-2016) 9,401,352 (Also granted in Germany, Patent No: DE102009030086)
  19. Mayank Shrivastava, Maryam Shojaei Baghini, Christian Russ, Harald Gossner, Ramgopal Rao, “High voltage semiconductor devices”, United States Patent (27-09-2016) 9,455,275. (Also granted in Germany, Patent No: DE102011050958).
  20. Mayank Shrivastava, Christian Russ, Harald Gossner, V. Ramgopal Rao, “Drain extended field effect transistors and methods of formation thereof”, United States Patent (09-05-2017) 9,647,069. (Also granted in Germany, Patent No: DE102012100767)
  21. Mayank Shrivastava, Christian Russ and Harald Gossner, “Tunable FIN-SCR for Robust ESD Protection”, United States Patent (28-03-2017) 9,608,098.
  22. Mayank Shrivastava and Christian Russ, “Semiconductor Devices And Arrangements Including Dummy Gates For Electrostatic Discharge Protection”, United States Patent No: (14-03-2017) 9,595,516.
  23. Mayank Shrivastava, Milova Paul, Christian Russ and Harald Gossner, “Non-planar Electrostatic Discharge (ESD) Protection Devices With Nano Heat Sinks”, US Patent No (11-06-2019): 10,319,662 (Indian Patent, Application No 201741003773, Filed on 1st Feb. 2017)
  24. Mayank Shrivastava, Milova Paul, Christian Russ and Harald Gossner, “Low Trigger and Holding Voltage Silicon Controlled Rectifier (SCR) For Non-Planar Technologies”, US Patent No (19-02-2019): 10,211,200 (Indian Patent, Application No 201741003772, Filed on 1st Feb. 2017)
  25. Mayank Shrivastava, Milova Paul and Harald Gossner, “Electrostatic Discharge (ESD) Protection Devices For ESD Robustness, Latch-Up and Hot Carrier Immunity”, US Patent No (19-11-2019): 10,483,258 (Indian Patent No. 376841) 
  26. Milova Paul, Mayank Shrivastava, Sampath Kumar, Christian Russ and Harald Gossner, “Dual Fin Silicon Controlled Rectifier (SCR) Electrostatic Discharge (ESD) Protection Device”, US Patent No (21-04-2020): 10,629,586 (Indian Patent, Application No 201741003771, Filed on 1st Feb. 2017)
  27. Mayank Shrivastava, Recess Gate Superjunction High-electron-mobility transistor (HEMT)”, US Patent No (02-02-2020): 10,553,712 (Indian Patent No: 522306,  Granted on 08th March 2024.)
  28. Mayank Shrivastava, Milova Paul and Harald Gossner, “FinFET SCR With SCR Implant Under Anode And Cathode Junctions”, US Patent No (04-02-2020): 10,535,762, (Indian Patent, Application No 201741006746, Filed on 25th Feb. 2017)
  29. Mayank Shrivastava, Sayak Dutta Gupta, Ankit Soni, Srinivasan Raghavan and Navakanta Bhat, “Enhancement Mode High Electron Mobility Transistor (HEMT)”, US Patent No (17-11-2020): 10,840,348 (Indian Patent Application 201741030570, August 2017)
  30. Rohit Soman, Ankit Soni, Mayank Shrivastava, S. Raghavan and Navakanta Bhat “High Electron Mobility Transistor (HEMT) with Resurf Junction”, US Patent Application No: US20200227543 A1  (Indian Patent No: 310947)
  31. Mayank Shrivastava and Vipin Joshi, “Doping and Trap Profile Engineering in GaN Buffer To Maximize AlGaN/GaN HEMT Epi Stack Breakdown Voltage”, US Patent No (08-06-2021):11,031,493 (Indian Patent Application 201841020899, Filled on June 5th 2019)
  32. Ankit Soni and Mayank Shrivastava, “Novel Drain Connected Field Plate HEMT Designs having Improved Performance”, Indian Patent No: 503229, Grant Date: 25th January 2024
  33. Ankit Soni and Mayank Shrivastava, “High Electron Mobility Transistor with improved performance and linearity”, Indian Patent No: 510450, Grant Date: 13th February 2024
  34. Ansh, Hemanjaneyulu Kuruva and Mayank Shrivastava, “Methods of Manufacturing 2-Dimentional Semiconductor Transistors”, Indian Patent No. 482722, Grant Date: 14th Dec. 2023
  35. N. S. Kranthi, K. Hemanjaneyulu, and Mayank Shrivastava, “A Field Effect Transistor (FET) with Improved Failure Threshold”, Indian Patent No. 441063, Grant Date: 28th July 2023
  36. Mayank Shrivastava, “Drain extended Tunnel FET”, US Patent Pending, Application No: US2021119044 (A1), Filed on: 23-Feb-17 (Indian Patent No: 470520, Filed on Feb 26th 2016, Grant Date: 20/11/2023
  37. Mayank Shrivastava and Kuruva Hemanjaneyulu “Fin enabled area scaled tunnel field Effect transistor”, Patent No: 364758, Grant Date: 16/04/2021.
  38. Mayank Shrivastava, “Drain extended Tunnel FET”, Indian Patent No: 470520, Grant Date: 20th Nov. 2023
  39. Rasik Rashid and Mayank Shrivastava, “High Electron Mobility Transistor Device”, Indian Patent (Application No: 202241038091) Grant No: 511048, Grant Date: 15th Feb 2024.
  40. Jatin and Mayank Shrivastava, “Metal Oxide Semiconductor Device Architecture with Uniform Finger Turn On And Method Thereof”, Indian Patent (Application No: 202341026588), Grant No: 509703, Grant Date: 12th Feb. 2024
  41. Mayank Shrivastava, “A Flexible, Adaptive Neuromorphic Synaptic Chip” Indian Patent No: 512480, Grant Date: 20th February 2024
  42. Adil Meersha, Mamta Khaneja and Mayank Shrivastava, A Method of Depositing Gate Dielectric on a 2D Material, Indian Patent Number: 517242, Grant Date: 8th Dec. 2024
  43. Adil Meersha, Mohan Lal and Mayank Shrivastava, Multilayer Graphene Contact for Monolayer Graphene Channel, Indian Patent Number: 560478, Grant Date: 17th May 2024
  44. Adil Meersha, Jaswant Singh Rawat and Mayank Shrivastava, Method to Selectively Etch h-BN, Indian Patent Number: 543182, Grant Date: 8th Dec. 2024
  45. Mayank Shrivastava and Rasik Rashid Malik, “Method to Tune Gate Work Function in p-GaN Gate e-mode HEMTs”, Indian Patent (Application No. 202341059980) Grant No: 563081, Grant Date: 21st March 2025. 
  46. Mayank Shrivastava and Anand Kumar Rai, “Doping and Activation Scheme for 2D Semiconductors”, (Application No. 202341059982), Grant No: 562843, Grant Date: 19th March 2025.
  47. Jatin and Mayank Shrivastava, “Nanosheet Drain Extended MOSFET”, Indian Patent (Application No: 202341007382) Grant No: 549891, Grant Date: 9th Sep. 2024.           
  48. Monishmurali M and Mayank Shrivastava, “Fin-Based SCR Architectures Having Distributed Current Configuration and Enhanced ESD Protection”, Indian Patent (Application No: 202041011502) Grant No: 532990, Grant Date: 15th April 2024.
  49. Monishmurali M and Mayank Shrivastava, “Low Capacitance FinFET SCR”, Indian Patent No. 566166, Grant Date: 14th May 2025
  50. Mayank Shrivastava and Rasik Rashid Malik, “A Method for Multiple Passivation Approach in p-GaN Gate e-Mode HEMTs”, Indian Patent (Application No. 202341059983), Patent No: 570711, Grant Date: 16 Sept 2025 (PCT-IN23-2048, filed on 06 Nov 2024).
  51. Utpreksh Patbhaje and Mayank Shrivastava, “Two-Dimensional (2D) Transition Metal Dichalcogenide Based Analog Memory Device”, Indian Patent (Application No. 202341059978), Patent No. 569113 Granted on 25 July 2025.